february 2011 ? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input nc7sp17 tinylogic ? ulp single buffer with schmitt trigger input features ? 0.9v to 3.6v v cc supply operation ? 3.6v over-voltage tolerant i/os at v cc from 0.9v to 3.6v ? propagation delay (t pd ): ? 4.0ns typical for 3.0v to 3.6v v cc ? 5.0ns typical for 2.3v to 2.7v v cc ? 6.0ns typical for 1.65v to 1.95v v cc ? 7.0ns typical for 1.40v to 1.60v v cc ? 11.0ns typical for 1.10v to 1.30v v cc ? 27.0ns typical for 0.90v v cc ? power-off high-impedance inputs and outputs ? static drive (i oh /i ol ): ? 2.6ma at 3.00v v cc ? 2.1ma at 2.30v v cc ? 1.5ma at 1.65v v cc ? 1.0ma at 1.40v v cc ? 0.5ma at 1.10v v cc ? 20a at 0.9v v cc ? quiet series? noise / emi reduction circuitry ? ultra small micropak? packages ? ultra low dynamic power description the nc7sp17 is a single buffer with schmitt trigger input from fairchild?s ultra low power (ulp) series of tinylogic?. ideal for applications where battery life is critical, this product is designed for ultra low power consumption within the v cc operating range of 0.9v to 3.6v v cc . the internal circuit is composed of a minimum of inverter stages, including t he output buffer, to enable ultra low static and dynamic power. the nc7sp17, for lower driv e requirements, is uniquely designed for optimized power and speed and is fabricated with an advanced cmos technology to achieve best-in-class s peed of operation, while maintaining extremely low cmos power dissipation. ordering information part number top mark package packing method nc7sp17p5x p17 5-lead sc70, eiaj sc- 88a, 1.25mm wide 3000 units on tape & reel nc7sp17l6x k4 6-lead micropak?, 1.00mm wide 5000 units on tape & reel nc7sp17fhx k4 6-lead, micropak2?, 1x1mm body, .35mm pitch 5000 units on tape & reel
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 2 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input notes: 1. tinylogic ulp and ulp-a with up to 50% less power consumption can extend ba ttery life significantly. 2. battery life=(v battery x i battery x 0.9) / (p device ) / 24hrs/day; where, p device =(i cc x v cc ) + (c pd + c l ) x v cc 2 x f. 3. assumes ideal 3.6v lithiu m ion battery with current rating of 900mah and derated 90% and device frequency at 10mhz, with c l =15pf load. figure 1. battery life vs. v cc supply voltage connection diagrams a ieee/iec 1 y figure 2. logic symbol pin configurations nc v cc 1 5 a 2 gnd y 3 4 1 nc 2 a 3 6 5 4 gnd v cc nc y figure 3. sc70 (top view) figure 4. micropak? (top through view) function table y=a input output a y l l h h l = low logic level h = high logic level pin definitions pin # sc70 pin # micropak name description 1 1, 5 nc no connect 2 2 a input 3 3 gnd ground 4 4 y output 5 6 v cc supply voltage
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 3 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 4.6 v v in dc input voltage -0.5 4.6 v v out dc output voltage high or low state (4) -0.5 v cc to +0.5 v v cc =0v -0.5 4.6 v i ik dc input diode current at v in < 0v -50 ma i ok dc output diode current v out < 0v -50 ma v out > v cc +50 i oh / i ol dc output source/sink current 50 ma i cc or ground dc v cc or ground current per supply pin 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature (sol dering, 10 seconds) +260 c p d power dissipation at +85c sc70-5 150 mw micropak?-6 130 micropak2?-6 120 esd human body model jedec: jesd22-a114 4000 v charged device model jedec: jesd22-c101 2000 note: 4. the i o maximum rating must be observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. typ. max. unit v cc supply voltage 0.9 3.6 v v in input voltage (5) 0 3.6 v v out output voltage high or low state 0 v cc v v cc =0v 0 3.6 i oh / i ol output current in i oh / i ol v cc =3.0v to 3.6v 2.6 ma v cc =2.3v to 2.7v 2.1 v cc =1.65v to 1.95v 1.5 v cc =1.40v to 1.60v 1.0 v cc =1.10v to 1.30v 0.5 v cc =0.9v 20.0 a t a free air operating tem perature -40 +85 c ? t / ? v minimum input edge rate v in =0.8v to 2.0v, v cc =3.0v 10 ns/v ? ja thermal resistance sc70-5 425 c/w micropak?-6 500 micropak2?-6 560 note: 5. unused inputs must be held high or low. they may not float.
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 4 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input dc electrical characteristics symbol parameter conditions v cc (v) t a =+25c t a =?40c to +85c units min. max. min. max. v p positive threshold voltage 0.90 0.30 0.60 0.30 0.60 v 1.10 0.40 1.00 0.40 1.00 1.40 0.50 1.20 0.50 1.20 1.65 0.70 1.50 0.70 1.50 2.30 1.00 1.90 1.00 1.90 3.00 1.50 2.60 1.50 2.60 v n negative threshold voltage 0.90 0.10 0.60 0.10 0.60 v 1.10 0.15 0.70 0.15 0.70 1.40 0.20 0.80 0.20 0.80 1.65 0.25 0.90 0.25 0.90 2.30 0.40 1.15 0.40 1.15 3.00 0.6 1.50 0.60 1.50 v h hysteresis voltage 0.90 0.07 0.50 0.07 0.50 v 1.10 0.08 0.60 0.08 0.60 1.40 0.09 0.80 0.09 0.80 1.65 0.10 1.00 0.10 1.00 2.30 0.25 1.10 0.25 1.10 3.00 0.60 1.80 0.60 1.80 v oh high level output voltage i oh =?20a 0.90 v cc ? 0.1 v cc ? 0.1 v 1.10 ? v cc ? 1.30 v cc ? 0.1 v cc ? 0.1 1.40 ? v cc ? 1.60 v cc ? 0.1 v cc ? 0.1 1.65 ? v cc ? 1.95 v cc ? 0.1 v cc ? 0.1 2.30 ? v cc ? 2.70 v cc ? 0.1 v cc ? 0.1 3.00 ? v cc ? 3.60 v cc ? 0.1 v cc ? 0.1 i oh =?0.5ma 1.10 ? v cc ? 1.30 0.75 x v cc 0.70 x v cc i oh =?1ma 1.40 ? v cc ? 1.60 1.07 0.99 i oh =?1.5ma 1.65 ? v cc ? 1.95 1.24 1.22 i oh =?2.1ma 2.30 ? v cc ? 2.70 1.95 1.87 i oh =?2.6ma 3.00 ? v cc ? 3.60 2.61 2.55 v ol low level output voltage i ol =20a 0.90 0.1 0.1 v 1.10 ? v cc ? 1.30 0.1 0.1 1.40 ? v cc ? 1.60 0.1 0.1 1.65 ? v cc ? 1.95 0.1 0.1 2.30 ? v cc ? 2.70 0.1 0.1 3.00 ? v cc ? 3.60 0.1 0.1 i ol =0.5ma 1.10 ? v cc ? 1.30 0.30 x v cc 0.30 x v cc i ol =1ma 1.40 ? v cc ? 1.60 0.31 0.37 i ol =1.5ma 1.65 ? v cc ? 1.95 0.31 0.35 i ol =2.1ma 2.30 ? v cc ? 2.70 0.31 0.33 i ol =2.6ma 3.00 ? v cc ? 3.60 0.31 0.33 i in input leakage current 0 ? v in ? 3.6v 0.90 to 3.60 0.1 0.5 a i off power off leakage current 0 ? (v in , v o ) ? 3.6v 0 0.5 0.5 a i cc quiescent supply current v in =v cc or gnd 0.90 to 3.60 0.9 0.9 a
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 5 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input ac electrical characteristics symbol parameter conditions v cc t a =25c t a =-40 to 85c units figure min. typ. max. min. max. t phl , t plh propagation delay c l =10pf, r l =1m ? 0.90 27.0 ns figure 5 figure 6 1.10 v cc 1.30 3.5 11.0 21.8 3.0 34.3 1.40 v cc 1.60 2.5 7.0 14.8 2.0 15.0 1.65 v cc 1.95 2.0 6.0 12.0 1.5 12.2 2.30 v cc 2.70 1.5 5.0 9.4 1.0 9.9 3.00 v cc 3.60 1.0 4.0 8.3 1.0 9.0 c l =15pf, r l =1m ? 0.90 30.0 1.10 v cc 1.30 4.0 11.0 22.8 3.5 37.3 1.40 v cc 1.60 3.0 8.0 15.5 2.5 16.5 1.65 v cc 1.95 2.5 6.0 12.6 2.0 13.6 2.30 v cc 2.70 2.0 5.0 9.9 1.5 10.8 3.00 v cc 3.60 1.5 4.0 8.7 1.0 9.5 c l =30pf, r l =1m ? 0.90 32.0 1.10 v cc 1.30 5.0 13.0 25.9 4.0 46.3 1.40 v cc 1.60 4.0 9.0 17.8 3.5 18.2 1.65 v cc 1.95 3.0 7.0 14.4 2.0 15.9 2.30 v cc 2.70 2.0 6.0 11.3 1.5 12.8 3.00 v cc 3.60 1.5 5.0 9.2 1.0 10.7 c in input capacitance 0 2 pf c pd power dissipation capacitance v in =0v or v cc , f=10mhz 0.90 to 3.60 8 pf figure 5. ac test circuit figure 6. ac waveforms for inverting and non-inverting functions symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0. 15v 1.5v 0.1v 1. 2v 0.1v 0.9v v mi 1.5v v cc / 2 v cc / 2 v cc / 2 v cc / 2 v cc / 2 v mo 1.5v v cc / 2 v cc / 2 v cc / 2 v cc / 2 v cc / 2
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 6 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input physical dimensions figure 7. 5-lead, sc70, eiaj sc-88a, 1.25mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf . package designator tape section cavity number cavity status cover type status p5x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 7 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input physical dimensions 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 8. 6-lead, micropak?, 1.0mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 8 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space cons trained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 6 54 0.35 (0.08) 4x side view figure 9. 6-lead, micropak2?, 1x1mm body, .35mm pitch package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf. package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2001 fairchild semiconductor corporation www.fairchildsemi.com nc7sp17 ? rev. 1.0.4 9 nc7sp17 ? tinylogic ? ulp single buffer with schmitt trigger input
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